| Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | |
| 3 | / { |
| 4 | |
| 5 | #address-cells = <0x2>; |
| 6 | #size-cells = <0x2>; |
| 7 | interrupt-parent = <0x1>; |
| 8 | model = "Generated"; |
| 9 | compatible = "arm,base"; |
| 10 | |
| 11 | memory@0 { |
| 12 | #address-cells = <0x2>; |
| 13 | #size-cells = <0x2>; |
| 14 | device_type = "memory"; |
| 15 | reg = <0x0 0x0 0x0 0x80000000>, |
| 16 | <0x00000008 0x80000000 0x0 0x80000000>; |
| 17 | }; |
| 18 | |
| 19 | cpus { |
| 20 | #address-cells = <0x2>; |
| 21 | #size-cells = <0x0>; |
| 22 | |
| 23 | cpu-map { |
| 24 | cluster0 { |
| 25 | core0 { thread0 { cpu = <&CPU_0>; }; }; |
| 26 | core1 { thread0 { cpu = <&CPU_1>; }; }; |
| 27 | core2 { thread0 { cpu = <&CPU_2>; }; }; |
| 28 | core3 { thread0 { cpu = <&CPU_3>; }; }; |
| 29 | }; |
| 30 | }; |
| 31 | |
| 32 | CPU_0: cpu@0 { |
| 33 | device_type = "cpu"; |
| 34 | compatible = "arm,armv8"; |
| 35 | reg = <0x0 0x0>; |
| 36 | enable-method = "spin-table"; |
| 37 | cpu-release-addr = <0x0 0x7f800>; |
| 38 | }; |
| 39 | |
| 40 | CPU_1: cpu@1 { |
| 41 | device_type = "cpu"; |
| 42 | compatible = "arm,armv8"; |
| 43 | reg = <0x0 0x1>; |
| 44 | enable-method = "spin-table"; |
| 45 | cpu-release-addr = <0x0 0x7f808>; |
| 46 | }; |
| 47 | |
| 48 | CPU_2: cpu@2 { |
| 49 | device_type = "cpu"; |
| 50 | compatible = "arm,armv8"; |
| 51 | reg = <0x0 0x2>; |
| 52 | enable-method = "spin-table"; |
| 53 | cpu-release-addr = <0x0 0x7f810>; |
| 54 | }; |
| 55 | |
| 56 | CPU_3: cpu@3 { |
| 57 | device_type = "cpu"; |
| 58 | compatible = "arm,armv8"; |
| 59 | reg = <0x0 0x3>; |
| 60 | enable-method = "spin-table"; |
| 61 | cpu-release-addr = <0x0 0x7f818>; |
| 62 | }; |
| 63 | }; |
| 64 | |
| 65 | interrupt-controller@af000000 { |
| 66 | compatible = "arm,gic-v3"; |
| 67 | #interrupt-cells = <0x3>; |
| 68 | #address-cells = <0x2>; |
| 69 | #size-cells = <0x2>; |
| 70 | ranges; |
| 71 | interrupt-controller; |
| 72 | #redistributor-regions = <0x1>; |
| 73 | reg = <0x0 0xaf000000 0x0 0x10000>, // GICD |
| 74 | <0x0 0xaf100000 0x0 0x100000>, // GICR |
| 75 | <0x0 0xac000000 0x0 0x2000>, // GICC |
| 76 | <0x0 0xac010000 0x0 0x2000>, // GICH |
| 77 | <0x0 0xac02f000 0x0 0x2000>; // GICV |
| 78 | interrupts = <0x1 9 0x4>; |
| 79 | linux,phandle = <0x1>; |
| 80 | phandle = <0x1>; |
| 81 | |
| 82 | its: msi-controller@2f020000 { |
| 83 | #msi-cells = <1>; |
| 84 | compatible = "arm,gic-v3-its"; |
| 85 | reg = <0x0 0xaf020000 0x0 0x20000>; // GITS |
| 86 | msi-controller; |
| 87 | }; |
| 88 | |
| 89 | }; |
| 90 | |
| 91 | refclk100mhz: refclk100mhz { |
| 92 | compatible = "fixed-clock"; |
| 93 | #clock-cells = <0>; |
| 94 | clock-frequency = <100000000>; |
| 95 | clock-output-names = "apb_pclk"; |
| 96 | }; |
| 97 | |
| 98 | refclk24mhz: refclk24mhz { |
| 99 | compatible = "fixed-clock"; |
| 100 | #clock-cells = <0>; |
| 101 | clock-frequency = <24000000>; |
| 102 | clock-output-names = "refclk24mhz"; |
| 103 | }; |
| 104 | |
| 105 | refclk1hz: refclk1hz { |
| 106 | compatible = "fixed-clock"; |
| 107 | #clock-cells = <0>; |
| 108 | clock-frequency = <1>; |
| 109 | clock-output-names = "refclk1hz"; |
| 110 | }; |
| 111 | |
| 112 | uart@9c090000 { |
| 113 | compatible = "arm,pl011", "arm,primecell"; |
| 114 | reg = <0x0 0x9c090000 0x0 0x1000>; |
| 115 | interrupts = <0x0 5 0x4>; |
| 116 | clocks = <&refclk24mhz>, <&refclk100mhz>; |
| 117 | clock-names = "uartclk", "apb_pclk"; |
| 118 | }; |
| 119 | |
| 120 | uart@9c0a0000 { |
| 121 | compatible = "arm,pl011", "arm,primecell"; |
| 122 | reg = <0x0 0x9c0a0000 0x0 0x1000>; |
| 123 | interrupts = <0x0 6 0x4>; |
| 124 | clocks = <&refclk24mhz>, <&refclk100mhz>; |
| 125 | clock-names = "uartclk", "apb_pclk"; |
| 126 | }; |
| 127 | |
| 128 | uart@9c0b0000 { |
| 129 | compatible = "arm,pl011", "arm,primecell"; |
| 130 | reg = <0x0 0x9c0b0000 0x0 0x1000>; |
| 131 | interrupts = <0x0 7 0x4>; |
| 132 | clocks = <&refclk24mhz>, <&refclk100mhz>; |
| 133 | clock-names = "uartclk", "apb_pclk"; |
| 134 | }; |
| 135 | |
| 136 | uart@9c0c0000 { |
| 137 | compatible = "arm,pl011", "arm,primecell"; |
| 138 | reg = <0x0 0x9c0c0000 0x0 0x1000>; |
| 139 | interrupts = <0x0 8 0x4>; |
| 140 | clocks = <&refclk24mhz>, <&refclk100mhz>; |
| 141 | clock-names = "uartclk", "apb_pclk"; |
| 142 | }; |
| 143 | |
| 144 | wdt@9c0f0000 { |
| 145 | compatible = "arm,sp805", "arm,primecell"; |
| 146 | reg = <0x0 0x9c0f0000 0x0 0x1000>; |
| 147 | interrupts = <0x0 0 0x4>; |
| 148 | clocks = <&refclk24mhz>, <&refclk100mhz>; |
| 149 | clock-names = "wdog_clk", "apb_pclk"; |
| 150 | }; |
| 151 | |
| 152 | rtc@9c170000 { |
| 153 | compatible = "arm,pl031", "arm,primecell"; |
| 154 | reg = <0x0 0x9c170000 0x0 0x1000>; |
| 155 | interrupts = <0x0 4 0x4>; |
| 156 | clocks = <&refclk1hz>; |
| 157 | clock-names = "apb_pclk"; |
| 158 | }; |
| 159 | |
| 160 | virtio-block@9c130000 { |
| 161 | compatible = "virtio,mmio"; |
| 162 | reg = <0 0x9c130000 0 0x200>; |
| 163 | interrupts = <0x0 42 0x4>; |
| 164 | }; |
| 165 | |
| 166 | virtio-p9@9c140000{ |
| 167 | compatible = "virtio,mmio"; |
| 168 | reg = <0x0 0x9c140000 0x0 0x1000>; |
| 169 | interrupts = <0x0 43 0x4>; |
| 170 | }; |
| 171 | |
| 172 | virtio-net@9c150000 { |
| 173 | compatible = "virtio,mmio"; |
| 174 | reg = <0 0x9c150000 0 0x200>; |
| 175 | interrupts = <0x0 44 0x4>; |
| 176 | }; |
| 177 | |
| 178 | virtio-rng@9c200000 { |
| 179 | compatible = "virtio,mmio"; |
| 180 | reg = <0 0x9c200000 0 0x200>; |
| 181 | interrupts = <0x0 46 0x4>; |
| 182 | }; |
| 183 | |
| 184 | timer { |
| 185 | compatible = "arm,armv8-timer"; |
| 186 | interrupts = <0x1 13 0xff08>, |
| 187 | <0x1 14 0xff08>, |
| 188 | <0x1 11 0xff08>, |
| 189 | <0x1 4 0xff08>; |
| 190 | clock-frequency = <100000000>; |
| 191 | }; |
| 192 | |
| 193 | aliases { |
| 194 | serial0 = "/uart@9c090000"; |
| 195 | serial1 = "/uart@9c0a0000"; |
| 196 | serial2 = "/uart@9c0b0000"; |
| 197 | serial3 = "/uart@9c0c0000"; |
| 198 | }; |
| 199 | |
| 200 | pmu { |
| 201 | compatible = "arm,armv8-pmuv3"; |
| 202 | interrupts = <0 60 4>, |
| 203 | <0 61 4>, |
| 204 | <0 62 4>, |
| 205 | <0 63 4>; |
| 206 | }; |
| 207 | |
| 208 | chosen { |
| 209 | bootargs = "earlycon console=ttyAMA0 loglevel=8 rootfstype=ext4 root=/dev/vda1 rw"; |
| 210 | stdout-path = "serial0"; |
| 211 | }; |
| 212 | }; |